The present invention relates to a semiconductor device, which has a superfine structure contributing to ultralarge-scale integration of a semiconductor integrated circuit and can operate at a high speed with its power dissipation reduced, and also relates to a method for fabricating the same.
As ultralarge-scale integration of semiconductor integrated circuits advances, miniaturization of MIS transistors is demanded more and more strongly. For that purpose, an MIS transistor with a shallow junction is now in high demand.
FIG. 5 illustrates a cross-sectional structure for a known MIS transistor with a shallow junction. A gate electrode 3 has been formed over a p-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween. In respective surface regions of the semiconductor substrate 1 that are located on both sides of the gate electrode 3 (i.e., regions to be source/drain regions), high-concentration dopant diffused layer 5, extended high-concentration dopant diffused layer 6 and pocket dopant diffused layer 7 are formed. The high-concentration dopant diffused layer 5 is formed to have a deep junction by diffusing an n-type dopant (e.g., arsenic) thereto. The extended high-concentration dopant diffused layer 6 is formed inside the high-concentration dopant diffused layer 5 by diffusing an n-type dopant (e.g., arsenic) thereto and has a junction shallower than that of the high-concentration dopant diffused layer 5. And the pocket dopant diffused layer 7 is located under the extended high-concentration dopant diffused layer 6 and has been formed by diffusing a p-type dopant (e.g., boron) thereto. Also, a sidewall 8 has been formed out of an insulating film on the side faces of the gate electrode 3.
Hereinafter, a method for fabricating the known MIS transistor will be described with reference to FIGS. 6(a) through 6(e).
First, as shown in FIG. 6(a), a gate electrode 3 is formed over a p-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween.
Next, arsenic and boron ions are implanted in this order as n- and p-type dopant ions, respectively, using the gate electrode 3 as a mask, thereby forming n- and p-type-ion implanted layers 6A and 7A, respectively, as shown in FIG. 6(b).
Then, a silicon nitride film is deposited over the entire surface of the semiconductor substrate 1 at a temperature of about 700° C., and then etched anisotropically, thereby forming a sidewall 8 on the side faces of the gate electrode 3 as shown in FIG. 6(c).
Subsequently, arsenic ions are implanted as n-type dopant ions using the gate electrode 2 and sidewall 8 as a mask. Then, annealing is conducted at a temperature between about 900° C. and about 1000° C. for about 10 seconds. In this manner, n-type high-concentration dopant diffused layer 5 with a deep junction, n-type extended high-concentration dopant diffused layer 6 located inside the high-concentration dopant diffused layer 5 and having a junction shallower than that of the high-concentration dopant diffused layer 5 and p-type pocket dopant diffused layer 7 located under the extended high-concentration dopant diffused layer 6 are formed as shown in FIG. 6(d).
Thereafter, a cobalt film and a titanium nitride film are deposited in this order to thicknesses of about 10 nm and about 20 nm, respectively, over the semiconductor substrate 1 by a sputtering process. Next, annealing is conducted at a temperature of about 550° C. for about 10 seconds. Then, the titanium nitride film and unreacted parts of the cobalt film are selectively etched away using a mixture of sulfuric acid, hydrogen peroxide and water. And then annealing is conducted at a temperature of about 800° C. for about 10 seconds. In this manner, a cobalt silicide layer 9 is formed to a thickness of about 30 nm on respective surfaces of the gate electrode 3 and high-concentration dopant diffused layer 5 in a self-aligned manner as shown in FIG. 6(e).
In the known MIS transistor fabrication process, the implant energy of arsenic ions for the n-type-ion implanted layer 6A, which is provided to form the extended highconcentration dopant diffused layer 6, is lowered to make the junction of the extended high-concentration dopant diffused layer 6 shallower and thereby increase the driving power of the MIS transistor. Also, to reduce the parasitic resistance of the source/drain regions, the implant dose of the arsenic ions is normally increased in this case.
However, if the n-type-ion implanted layer 6A is formed by implanting the arsenic ions at a high implant dose and with a low implant energy, then transient enhanced diffusion (TED) of arsenic and boron (i.e., dopants for the n-type-ion implanted layer 6A and pocket dopant diffused layer 7) occurs during the lower-temperature (e.g., about 700° C.) annealing process to be carried out after that to form the sidewall 8. In that case, the extended high-concentration dopant diffused layer 6 and pocket dopant diffused layer 7 cannot be formed to have respective shallow junctions as designed. It should be noted that the transient enhanced diffusion is a phenomenon in which an introduced dopant unintentionally diffuses at such a rate as exceeding its diffusion coefficient in thermal equilibrium state. This is because point defects, existing in excessive numbers between lattice sites, and the dopant interact with each other to mutually enhance their diffusion.
FIG. 7 illustrates profiles of the dopant ions, which have been introduced to form the extended high-concentration dopant diffused layer 6 and pocket dopant diffused layer 7, in the depth direction (i.e., the direction indicated by the line A–A′ in FIG. 5). As can be seen from FIG. 7, the profile of arsenic for the extended high-concentration dopant diffused layer 6 as plotted in the depth direction shows that its diffusion is rather deep due to the transient enhanced diffusion effects during the anneal. Boron for the pocket dopant diffused layer 7 has also been much affected by the transient enhanced diffusion so that its profile has lost sharpness. As also can be seen from FIG. 7, according to the known method, it is difficult to form the extended high-concentration dopant diffused layer and pocket dopant diffused layer just as intended, i.e., so that these layers have shallow and sharp dopant profiles and exhibit excellent short channel effects.